VCTCXO / TCXO

FEATURE
- Typical 5.0 x 3.2 x 1.55 mm ceramic SMD package.

- ±0.2ppm, -40

o
C ~+85

o
C ; ±0.05ppm, -10

o o
C +70 C

- CMOS and Clipped Sine wave (without DC-cut capacitor) output optional.
TYPICAL APPLICATION
- Base Stations, Stratum 3
- Femtocell RoHS Compliant Standard
DIMENSION (mm) SOLDER PAD LAYOUT (mm)










☆ To ensure optimal oscillator performance, Place a by-pass capacitor of 0.1µF as close to the part as possible between Vdd and GND pads.


ELECTRICAL SPECIFICATION

Parameter 5.0V 3.3V
Unit
Min. Max. Min. Max.
Supply Voltage Variation (VDD) 5% 4.75 5.25 2.97 3.63 V
Frequency Range 10 40 10 40
MHz
Standard Frequency (for CMOS) 10, 12.8, 19.2, 20, 26, 30.72
Standard Frequency (for Clipped Sine) 10, 12.8, 19.2, 20, 26, 30.72
Frequency Tolerance* - ±2.0 - ±2.0 ppm
Frequency Stability
Vs Supply Voltage (±5%) change (CMOS) - ±0.2 - ±0.2 ppm
Vs Load (±10%) change - ±0.2 - ±0.2
Vs Aging (after 1 year) - ±1.0 - ±1.0 ppm/year
Supply Current (CMOS output) - 6 - 6 mA
Supply Current (Clipped Sine Wave) - 3.5 - 3.5
Output Level (CMOS) Output High (Logic “1”) 90% VDD - 90% VDD - V
Output Low (Logic “0”) - 10% VDD - 10% VDD
Duty 45 55 45 55 %
Output Level (Clipped Sine Wave) 0.8 - 0.8 - Vp-p
Load (CMOS) 15pF 15pF
Load (Clipped Sine Wave) 10KΩ//10pF 10KΩ//10pF
Control Voltage Range (VCTCXO) 0.5 2.5 0.5 2.5 V
Pulling Range (VCTCXO) ±5.0 ±10.0 ±5.0 ±10.0 ppm
Vc Input Impedance (VCTCXO) 100 - 100 - KΩ
Phase Noise @ 12.8 MHz
100 Hz -125 -125
dBc/Hz
1 KHz -145 -145
10 KHz -150 -150
Start Time - 2 - 2 mSec
Storage Temp. Range -55 125 -55 125 o
C
Standard frequencies are frequencies which the crystal has been designed and does no imply a stock position
o
*Frequency at 25 C 1 hour after reflow
Packing: Tape & Reel, 1000/3000 pcs per Reel.
FREQ. STABILITY vs. TEMP. RANGE






* O: Available

△:Conditional X: Not available






Specifications subject to change without notice. Rev(3)03/2013